1. Field
The present application relates to an apparatus and method for displaying graphics, and more particularly, to an apparatus and method that can accelerate the display of graphics.
2. Background Art
In clinical practice, monitor (e.g. patient monitor) plays an important role in diseases diagnosis because it can display various human physiological parameters dynamically.
In order to provide more comprehensive and accurate reflection of human physiological conditions, the monitoring function of a modern monitor has been extended from the ECG (electrocardiogram) monitoring to measurement of various human physiological parameters, such as blood pressure, respiration rate, Saturation of Pulse Oxygen (SpO2) and so on. However, the more physiological parameters are shown on the monitor, the higher a resolution is needed for the monitor, that is, the more video data is needed to generate images. Therefore, how to accurately display large numbers of data reflecting physiological parameters in real time has become a significant criterion for evaluating the performance of a patient monitor.
For a modern monitor, information display speed can only be improved limitedly by any of increasing the frequencies of processor and system bus, applying high-performance data bus configuration (e.g., PCI-Express) and employing general display driver IC chip, while the costs for the monitor are notably increased. Further, it is difficult for such monitor to provide flexible extension of displayed physiological parameters according to the user's need.
Recently, a display memory (also referred to as Video RAM) mapping technology has been proposed to improve the information display speed. The technology, based on design of the state machine, achieves transform operations for mapping the graphics data to be displayed into image information for display memory by means of the FPGA (Field Programmable Gate Array).
FIG. 1 shows an apparatus using the display memory mapping technology to display graphics in existing monitors. The apparatus comprises: a data source 5, an embedded processor for example, to generate graphics or image data to be displayed; a memory 10 to store the graphics data that comprises screen coordinates and chroma data for graphics such as point, line, rectangle and so on, wherein, the screen coordinates can be Cartesian coordinates for example and the chroma data comprises the data such as color or gray level; a transform module 20, based on the trigger condition of a state machine, to transform the graphics data of different graphics into image information for the display memory, the image information comprising mapping addresses transformed from the screen coordinates and chroma information transformed according to the color and gray level data; a display memory read/write module 30, based on the mapping addresses, to store image information with regard to the corresponding pixels on the display screen into a display memory 40; and a display timing control module 50, under the control of which, the image information read by the display memory read/write module 30 from the display memory is presented on the screen of a display 60 as the brightness or color of pixels at corresponding positions.
However, the operation speed of the apparatus for displaying graphics as shown in FIG. 1 will be seriously affected when the state number of the state machine is increased. Moreover, as the state number of the state machine increases, the development and maintenance costs of the apparatus will grow substantially.
Then, a configuration is proposed which, by adopting a state partitioning approach and employing a plurality of transform modules corresponding to different states to execute transform operations respectively, improves the graphics displaying speed. In an apparatus adopting the configuration for displaying graphics, an orthogonal algorithm is used to partition the states. However, the complexity of the orthogonal algorithm will grow rapidly with the increased number of the partitioned states.
Hereinafter, the above two apparatus for displaying graphics will be described by constructing mathematical models.
First, in a mathematical model corresponding to the apparatus for displaying graphics as shown in FIG. 1, where supposed that one transform module is used to execute transform operations, the operation of transforming each graphics data into image information can be denoted as C(xi, t), wherein i denotes the sequence number of the graphics data to be transformed. If there are six graphics data, they will be denoted as C(x1, t), C(x2, t) . . . C(x6, t) respectively. Apparently, at the same time t, the pixels corresponding to the image information of the six graphics data will be located at different positions on the dimensional axis x. This apparatus for displaying graphics will not cause data overlapping problem when performing the transformations. However, its operation speed, as described above, will be seriously affected when the state number of the state machine is increased.
In a mathematical model corresponding to the apparatus for displaying graphics adopting a state partitioning approach and employing a plurality of transform modules to execute transform operations, the operation of transforming each graphics data into image information can be denoted as C(Xi, t), wherein, Xi is an n-dimensional space vector; n denotes the number of the transform modules configured in parallel according to different graphics types; and i denotes the sequence number of the graphics data to be transformed. Provided that there are six graphics data and meanwhile three transform modules being configured in parallel according to three types of graphics such as point, line and rectangle, then the image information corresponding to the 6 graphics data will be denoted as C(X1, t), C(X2, t) . . . C(X6, t) respectively, wherein, each C(Xi, t) is a six-dimensional space vector and is a function of time t. It is known from this mathematical model that, in order to prevent the data overlapping problem, every two n-dimensional space vectors must be guaranteed orthogonal when “t”s thereof are the same, i.e., at the same time. Moreover it is known from mathematical principles that the complexity of the orthogonal algorithm is proportional to n2. When the number of transform modules in use increases with the types of graphics, the need for determining whether the n-dimensional space vectors are orthogonal, no matter it is to be executed before or after the transform operations, will surely lead to a substantially complex logic circuit, and the FPGA for executing the operation will become a bottle-neck for the graphics display due to lack of resources.
Consequently, there exists a need for a novel and economical apparatus for displaying graphics that will not be affected by the state number of the state machine and can display graphics quickly.